Annotated edit history of
PCI version 5, including all changes.
View license author blame.
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AristotlePagaltzis |
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An [Acronym] for __P__eripheral __C__omponent __I__nterconnect. |
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PhilMurray |
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The major [Bus] in use by modern computers as specified by [PCI-SIG|http://www.pcisig.org]. Available in 32bit or 64bit and 33Mhz or 66Mhz flavours. Now superseeded by PCI-X and PCI-Express. |
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PCI-X is available in 64bit and 66, 100, 133, 266[2] and 533Mhz[2] variants. Mostly only used in servers for various peripheral cards that require high bandwidth like RAID, Gigabit Ethernet and Fibre Channel HBA cards. |
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IanMcDonald |
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PCI-Express does away with the traditional [Bus] architecture of PCI and replaces it with a packet-based point-to-point architecture. Each slot is available as a number of full-duplex lanes from 1 to 32 combined to form a link that's connected to a switch. Each lane is capable of transmitting 2.5Gbps in each direction. 16x slots, at 40Gbps, are being used to replace [AGP] slots for graphics adapters. PCI-Express is backwards compatible with PCI from a software point of view, so an [OperatingSystem] does not need any modification to support PCI-Express hardware. |
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PhilMurray |
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[2]: Since version 2.0 of the PCI-X specification |
