Differences between current version and predecessor to the previous major change of CAS.

Other diffs: Previous Revision, Previous Author, or view the Annotated Edit History

Newer page: version 4 Last edited on Tuesday, May 10, 2005 5:10:48 pm by CraigBox
Older page: version 2 Last edited on Tuesday, May 10, 2005 11:36:22 am by MichaelBordignon Revert
@@ -1,4 +1,6 @@
+[Acronym] for __C__olumn __A__ccess __S__trobe.  
 Lower = faster = better 
 RAM is organized into rows and columns, and is accessed by electrical signals called strobes, which are sent along rows to the columns; when data is needed, the CPU activates the RAS (Row Access Strobe) line to specify the row where data is to be found (high bits), then, after a short time, the CAS, or Column Access Strobe, to specify the column (low bits). After that, the data goes to the output line and to its destination on the next clock tick. In other words, the Column Address Strobe dictates how many clocks the memory waits before sending data on. All registers should be full, or errors will result, which means a longer wait to make sure, and slower operation. The shorter the cycle length, the faster the machine runs, at the expense of stability and data. 
@@ -15,4 +17,8 @@
 The first set would be for EDO and the second for Fast Page Mode RAM. The 430HX chipset can use lower figures than the VX. The idea is to keep the figures as low as possible, consistent with your machine working properly. Note that EDO is only faster when being read from; writes take place at the same speed as FPM RAM. 
+Part of CategoryHardware