Differences between current version and revision by previous author of RISC.
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| Newer page: | version 5 | Last edited on Tuesday, August 12, 2003 4:48:19 pm | by AristotlePagaltzis | |
| Older page: | version 4 | Last edited on Sunday, August 10, 2003 4:01:24 pm | by JamieCurtis | Revert |
@@ -1,7 +1,7 @@
-An [Acronym] for __R__educed __I__nstruction __S__et __C__omputing (or Chip?).
+An [Acronym] for __R__educed __I__nstruction __S__et __C__omputing
Basically the idea is that the chip has relatively few machine level op codes, which makes the chip easier to design, and physically smaller. Typically the smaller instruction set allows the chip to do fewer operations, but can do each individual operation much quicker than a larger, "bloated" chip. RISC [CPU]s typically have much lower power consumption than larger chips.
Examples of RISC CPUs are [ARM], [SPARC], [MIPS] and [PowerPC].
-Compare and contrast with [CISC]. (C = complex). In the 1980s it was assumed that the natural superiority of RISC design would see CISC CPUs
die out...
+Compare and contrast with [CISC]. (C = complex). In the 1980s it was assumed that the natural superiority of RISC design would see CISC [CPU]s
die out... what happened in reality was that most [CPU] architectures developed into crossbreeds between the RISC and [CISC] philosophies
.
